1. Field of the Invention
This invention relates to initializing of test mode functions, and more particularly, to a test mode muxing scheme that can reduce channel routing.
2. Description of the Prior Art
A primary concern of modern semiconductor devices is reducing the size of a die to achieve smaller devices. Semiconductor memories usually include a test-mode circuit. In this technology, when a memory is initialized, a test mode will be entered, which involves sending test mode signals from a variety of efuses to address blocks in order to verify that all circuits are operational. After all blocks are verified, the test mode signals and efuses are no longer needed.
Please refer to FIG. 1 which shows a conventional die circuit layout 100. The die 100 comprises a block of efuses 110 which provide a plurality of test-mode signals that are respectively routed through a plurality of decoders 121, 123, 125, 127 and latches 122, 124, 126, 128. The decoders and latches comprise a test-mode (TM) block 120, which is disposed on the die 100 close to the efuses 110. The TM block 120 then routes these latched signals to the correct individual address blocks 130, 140, 150, 160, where they will be used to test the workings of each block. As the TM block 120 is positioned relatively far from the address blocks, as shown in FIG. 1, a significant surface area of the die 100 is required for this signal routing. In some cases, the signals are routed over half the die 100, which wastes surface area that could be used for other circuitry. Furthermore, these signals are only required during power-up. As die reduction is critical in the field, a more efficient system is desired.